Title: Systems Hardware Architect
Analog Circuit
Experience in entire Analog IP development including circuit design, layout, AMS verification and characterization
2) Must have led the entire Analog IP development cycle and team
3) Circuit Design implementation of IPs including LDOs, Band Gap reference, Current Generators, POR, ADC/DACs, PLLs, Oscillators, General Purpose IOs, Temperature sensor, SERDES, PHYs, Die to Die interconnect, High-speed IOs etc
4) Analog/custom layout design in advanced CMOS process
5) Ability to understand design constraints and implement high-quality layouts
6) Conceptualize and implement chip-level mixed signal simulation environments (testbenches, run scripts, etc...)
7) Characterization
8) Hands-on experience on lower FINFET technology nodes and design/PPA trade offs
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Do
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Experience in entire Analog IP development including circuit design, layout, AMS verification and characterization
2) Must have led the entire Analog IP development cycle and team
3) Circuit Design implementation of IPs including LDOs, Band Gap reference, Current Generators, POR, ADC/DACs, PLLs, Oscillators, General Purpose IOs, Temperature sensor, SERDES, PHYs, Die to Die interconnect, High-speed IOs etc
4) Analog/custom layout design in advanced CMOS process
5) Ability to understand design constraints and implement high-quality layouts
6) Conceptualize and implement chip-level mixed signal simulation environments (testbenches, run scripts, etc...)
7) Characterization
8) Hands-on experience on lower FINFET technology nodes and design/PPA trade offs
͏
-
Experience in entire Analog IP development including circuit design, layout, AMS verification and characterization
2) Must have led the entire Analog IP development cycle and team
3) Circuit Design implementation of IPs including LDOs, Band Gap reference, Current Generators, POR, ADC/DACs, PLLs, Oscillators, General Purpose IOs, Temperature sensor, SERDES, PHYs, Die to Die interconnect, High-speed IOs etc
4) Analog/custom layout design in advanced CMOS process
5) Ability to understand design constraints and implement high-quality layouts
6) Conceptualize and implement chip-level mixed signal simulation environments (testbenches, run scripts, etc...)
7) Characterization
8) Hands-on experience on lower FINFET technology nodes and design/PPA trade offs
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Deliver
No. | Performance Parameter | Measure |
1. | Product design, engineering and implementation | CSAT, quality of design/ architecture, FTR, delivery as per cost, quality and timeline, POC review and standards |
2. | Capability development | % trainings and certifications completed, mentor technical teams, Thought leadership content developed (white papers, Wipro PoVs) |
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