Title: Design Verification Engineer
Design Verification Engineer͏
Key Responsibilities:
- Strong understanding of SV and UVM and good debugging skills.
- Understanding of AMBA protocols.
- Understand design specs and develop test plans based on functional and architectural requirements
- Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testing
- Develop directed and random testcases, perform coverage analysis, and close functional/code coverage
- Debug simulation failures and work closely with RTL designers to resolve issues
- Execute regression runs, analyze results, and contribute to continuous improvements
- Integrate and run power-aware simulations, low power checks, and work with UPF/CPF as needed
- Collaborate with DFT/PD/RTL teams and post-silicon validation to ensure design quality across domains
- Document test environments, test plans, and results for internal and external reviews
Expected annual pay for this role ranges from $140,000 to $1,73,000 . Based on the position, the role is also eligible for Wipro’s standard benefits including a full range of medical and dental benefits options, disability insurance, paid time off (inclusive of sick leave), other paid and unpaid leave options.
Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.
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