Title: Senior Design Verification Engineer
Senior Design Verification Engineer
UVM with C, C++ Coding Skills, System Verilog, CPU
AMBA protocols – AXI with addition one or more protocols like i3c, SPI, OCP etc
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Mandatory Skills: VLSI HVL Verification .
Experience: 8-16 Years .
Expected annual pay for this role ranges from $80,000 to $1,73,000 . Based on the position, the role is also eligible for Wipro’s standard benefits including a full range of medical and dental benefits options, disability insurance, paid time off (inclusive of sick leave), other paid and unpaid leave options.
Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.
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