Job Description
Job Title:  Design Verification Architect
City:  Bengaluru
State/Province:  Karnataka
Posting Start Date:  10/18/26
Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com.

Job Description

Role Purpose


The purpose of the role is to design, and architect VLSI and Hardware based products and enable delivery teams to provide exceptional client engagement and satisfaction.
 

D͏esign Verification Architect

 

Experience

15+ years

Location

Bangalore, Hyderabad, Kochi, Pune, Chennai

Domain

ASIC / SoC – Turnkey Silicon

Employment

Full-time

The Role

Define verification strategy and architect scalable UVM environments for subsystem and SoC designs, owning coverage closure and verification signoff.

What You Will Do

  • Define the end-to-end verification strategy, plans, coverage models and signoff criteria.
  • Architect reusable, scalable SystemVerilog/UVM testbenches and VIP at subsystem and SoC level.
  • Drive constrained-random, assertion-based (SVA), formal, power-aware (UPF) and gate-level verification.
  • Establish regression, automation and quality metrics infrastructure.
  • Lead technical reviews of test plans, testbench architecture and coverage closure.
  • Work with RTL, DFT, PD and firmware teams; support emulation and post-silicon debug.

What You Bring

  • 15+ years in ASIC/SoC verification, with ownership of subsystem and chip-level verification through tape-out.
  • Expert SystemVerilog, UVM, SVA and coverage-driven verification.
  • Experience leading DV teams and being the technical escalation point.
  • Strong with high-speed and bus protocols such as PCIe, DDR/LPDDR, Ethernet, AMBA, UCIe.
  • Hands-on with regression management, debug and gate-level / power-aware simulation.
  • Scripting in Python, Perl or Shell.

Good to Have

  • Formal verification and emulation / FPGA prototyping
  • Hardware/software co-verification
  • Post-silicon bring-up exposure

D͏esign Verification Architect

  • Experience

    15+ years

    Location

    Bangalore, Hyderabad, Kochi, Pune, Chennai

    Domain

    ASIC / SoC – Turnkey Silicon

    Employment

    Full-time

    The Role

    Define verification strategy and architect scalable UVM environments for subsystem and SoC designs, owning coverage closure and verification signoff.

    What You Will Do

    • Define the end-to-end verification strategy, plans, coverage models and signoff criteria.
    • Architect reusable, scalable SystemVerilog/UVM testbenches and VIP at subsystem and SoC level.
    • Drive constrained-random, assertion-based (SVA), formal, power-aware (UPF) and gate-level verification.
    • Establish regression, automation and quality metrics infrastructure.
    • Lead technical reviews of test plans, testbench architecture and coverage closure.
    • Work with RTL, DFT, PD and firmware teams; support emulation and post-silicon debug.

    What You Bring

    • 15+ years in ASIC/SoC verification, with ownership of subsystem and chip-level verification through tape-out.
    • Expert SystemVerilog, UVM, SVA and coverage-driven verification.
    • Experience leading DV teams and being the technical escalation point.
    • Strong with high-speed and bus protocols such as PCIe, DDR/LPDDR, Ethernet, AMBA, UCIe.
    • Hands-on with regression management, debug and gate-level / power-aware simulation.
    • Scripting in Python, Perl or Shell.

    Good to Have

    • Formal verification and emulation / FPGA prototyping
    • Hardware/software co-verification
    • Post-silicon bring-up exposure

͏

Deliver

No. Performance Parameter Measure
1. Product design, engineering and implementation CSAT, quality of design/ architecture, FTR, delivery as per cost, quality and timeline, POC review and standards
2. Capability development % trainings and certifications completed, mentor technical teams, Thought leadership content developed (white papers, Wipro PoVs)

 

͏

 

Mandatory Skills: System Verilog - SV .

 

Experience: >10 YEARS .

 

Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention.
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