Job Description
Job Title:  DFT Engineer
City:  Mountain View
State/Province:  California
Posting Start Date:  6/18/26
Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com.
Job Description: 

Job Description

Job Description
We are seeking a DFT Engineer with hands-on experience in Scan, MBIST, ATPG generation, and pattern simulation for complex SoC/IP designs.
Key Responsibilities
• Develop and implement Design-for-Test (DFT) architecture for IPs and SoCs.
• Perform Scan insertion and Scan chain verification.
• Integrate and validate MBIST solutions for embedded memories.
• Generate ATPG patterns for stuck-at, transition, and other manufacturing fault models.
• Execute ATPG simulation and pattern verification to ensure coverage and pattern quality.
• Analyze and improve fault coverage while reducing pattern count.
• Debug DFT-related issues during implementation and verification.
• Collaborate with RTL, Physical Design, Verification, and Test Engineering teams.
• Support silicon bring-up and production test activities when required.
Required Skills
• Strong understanding of DFT fundamentals.
• Hands-on experience in:
o Scan Architecture
o Scan Insertion
o Scan Compression
o MBIST Integration
o ATPG Pattern Generation
o ATPG Simulation
o Fault Coverage Analysis
o DFT Verification
• Experience with industry-standard DFT tools such as:
o Tessent
o Synopsys DFT Compiler
o TetraMAX / TestMAX ATPG
o Modus (preferred)
• Good knowledge of Verilog/SystemVerilog and simulation environments.
• Familiarity with manufacturing test concepts and silicon debug.
Preferred Qualifications
• Experience with large SoC or CPU/GPU designs.
• Knowledge of IJTAG, Boundary Scan (JTAG), LBIST, and Test Compression.
• Experience supporting post-silicon test and yield improvement activities.



 
Mandatory Skills: VLSI Design For Testability - DFT .

 

Experience: 3-5 Years .

 

The expected compensation for this role ranges from $45,000 to $121,000 .

 

Final compensation will depend on various factors, including your geographical location, minimum wage obligations, skills, and relevant experience. Based on the position, the role is also eligible for Wipro's standard benefits including a full range of medical and dental benefits options, disability insurance, paid time off (inclusive of sick leave), other paid and unpaid leave options.

 

Applicants are advised that employment in some roles may be conditioned on successful completion of a post-offer drug screening, subject to applicable state law.

 

Wipro provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws. Applications from veterans and people with disabilities are explicitly welcome.

 

Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention.
Information at a Glance

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