Job Description

Role Purpose
The purpose of this role is to lead the VLSI development and design of the system by defining the various functionalities, architecture, layout and implementation for a client 

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We are looking for Senior Physical Design Engineers with strong hands‑on experience in RTL‑to‑GDSII implementation. The engineer should be capable of independently owning two or more design partitions of varying complexity.

The selected PEO will have end‑to‑end ownership of the Physical Design flow, starting from synthesis through PNR, Clock Tree Synthesis (CTS), timing closure, and physical signoff.

Key Expectations

• Own and deliver RTL2GDSII for multiple partitions
• Handle complete PD flow including:
• Synthesis
• Floorplanning, Placement, CTS
• Routing and optimization
• Timing closure across all corners
• Perform and close signoff checks, including:
• VCLP
• IR / RV
• FEV
• LVS / DRC
• Work independently with minimal supervision
• Drive issue resolution for timing, congestion, power, and physical verification
• Communicate effectively with internal teams and stakeholders

Skill Requirements

• Strong hands‑on experience in:
• PNR
• Timing closure
• Physical signoff
• Proven ability to own blocks independently
• Good communication and coordination skills

Experience

• 5+ years of relevant experience in ASIC Physical Design

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• Senior Physical Design Engineer (RTL2GDSII)
• Looking for PD engineers with 5+ years experience to independently own RTL‑to‑GDSII for multiple partitions.
• Strong hands‑on expertise in PNR, CTS, timing closure, and physical signoff.
• Must have experience with VCLP, IR/RV, FEV, LVS/DRC.
• Good communication skills and ability to work independently.