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This engineer plays a key role in SoC Design flow, he/she will mainly focus on DFX SMS design, verification and post-silicon ATE pattern debug tasks. Moreover, he/she is expected to provide strong technical supports for Feint, PD, SoC DV and other DFX functional domain owners.

THE PERSON:

Good team worker with solid mbist design and verification experience. Knowledge reservation on STA/Verification/RTL quality check will be a strong plus.

KEY RESPONSIBILITIES:

· Implement SoC DFX SMS design on SRAM, ROM, Latch Arrays, etc.

· Develop and verify tile level and chip level bist and memory repair test cases.

· Develop and verify high coverage and cost-effective test patterns for production test.

· Support DFX SMS design quality check and documentation tasks.

· Support DFX silicon bring up and ATE test.

PREFERRED EXPERIENCE:

· Solid background on process, device or ASIC design.

· Proven knowledge and expertise on two or more fields of SCAN, MBIST, RTL design, STA, Verification and Emulation.

· Experience in Synthesis, formal/LEC, or CDC will be a plus.

· Prior SoC project test experience is a plus.

· Strong programming and scripting skills in Perl, Tcl or Python will be a strong plus.

· Good verbal, written and communication skill in English and Mandarin.

· Good teamwork spirit and self-driven.

ACADEMIC CREDENTIALS:

· . Master degree with 1 year or Bachelor with 3 years experience at least

LOCATION:

· Penang

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers and will consider all applicants without regard to race, marital status, sex, age, color, religion, national origin, veteran status, disability or any other characteristic protected by law. EOE/MFDV