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This engineer plays a key role in SoC DV flow, he/she will mainly focus on chip level DFX functions verification tasks. Moreover, he/she is expected to collaborate with test engineering team to support DFX silicon bring up and ATE test.
THE PERSON:
Good team worker with solid Verilog RTL design and verification knowledge/experience. Knowledge reservation on System_Verilog/UVM/Modeling/Scan/BIST will be a strong plus.
KEY RESPONSIBILITIES:
· Cutting-edge test strategies study and implementation.
· SoC DFX test plan development based on design specification and DFX feature list.
· Responsible for SoC level DFX test case development and verification.
· Support DFX Cross-die Co-sim simulation and power-aware simulation tasks.
· Support DFX silicon bring up and ATE test.
PREFERRED EXPERIENCE:
· Solid background on process, device or ASIC design.
· Strong technical background in Verilog coding and testbench development.
· Experience in System Verilog and UVM will be a strong plus.
· Good knowledge on JTAG 1149.1, 1500 and 1687 protocols will be a strong plus.
· Good knowledge on DFT Scan/BIST will be a strong plus.
· Strong programming and scripting skills in Perl, Tcl or Python will be a strong plus.
· Good communication skills and self-driven, willing to learn/share.
ACADEMIC CREDENTIALS:
· Master degree with 1 years or Bachelor with 3 years experience at least.
LOCATION:
· Penang
AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers and will consider all applicants without regard to race, marital status, sex, age, color, religion, national origin, veteran status, disability or any other characteristic protected by law. EOE/MFDV
Experience: 3-5 Years .
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