Job Description
Job Title:  VLSI Engineer - L2
Req Id:  90945
City:  Penang
State/Province:  Penang
Posting Start Date:  8/22/25
Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com.
Job Description: 

Job Description

To work independently on block/IP levels analog layout design from schematic.

Estimating the Area, Optimizing Floorplan, Routing and Verifications.

Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below.

Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts.

Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally.

 

Key Responsibilities:

 

Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimization, routing, and layout verification.

Perform LVS (Layout vs. Schematic) and DRC (Design Rule Check) debugging for advanced FinFET technology nodes (5nm, 7nm, 10nm, 14nm and below).

Ensure layout quality by applying principles of matching, electromigration (EM), electrostatic discharge (ESD), latch-up prevention, shielding, parasitic management, and short channel effects.

Utilize industry-standard EDA tools such as Cadence Virtuoso Editor and Calibre RVE for layout and verification tasks.

 

Primary Skills :

Analog Layout Design (Block/IP level)

LVS/DRC Debugging

FinFET Technology Node Experience (5nm, 7nm, 10nm, 14nm and below)

EDA Tools

Cadence Virtuoso Editor

Calibre RVE

Layout Optimization

Area estimation

Floorplanning

Routing

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Mandatory Skills: Analog Layout .

 

Experience: 1-3 Years .

 

Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.
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