Job Description
Job Title:  VLSI LEAD L1
City:  Penang
State/Province:  Penang
Posting Start Date:  5/13/26
Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com.
Job Description: 

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THE ROLE:

This leader plays a key role in SoC DV flow, he/she will mainly focus on chip level DFX functions verification tasks and drive the DV team’s execution with high quality in a good schedule manner. Moreover, he/she is expected to support post-silicon ATE test to achieve the desired silicon bring up target.

 

THE PERSON:

Good team worker with solid Verilog RTL design and verification knowledge/experience. Knowledge reservation on System_Verilog/UVM/Modeling/Scan/BIST will be a strong plus.

 

 

KEY RESPONSIBILITIES:

· Cutting-edge test strategies study and implementation.

· Allocate DFX DV Resource and organize periodic DFX DV quality review.

· Responsible for key design milestone DFX DV checklist signoff.

· SoC DFX test plan development based on design specification and DFX feature list.

· Responsible for SoC DFX testbench development and maintenance.

· Responsible for SoC level DFX test case development and verification.

· Support DFX Cross-die Co-sim simulation and power-aware simulation tasks.

· Collaborate with test engineering team to support DFX silicon bring up and ATE test.

· Drive the DFX DV verification flow robustness and efficiency enhancement.

 

PREFERRED EXPERIENCE:

· Solid background on process, device or ASIC design.

· Strong technical background in Verilog coding and testbench development.

· Good knowledge on JTAG 1149.1, 1500 and 1687 protocols will be a plus.

· Experience in System Verilog and UVM will be a plus.

· Good knowledge on DFT Scan/BIST will be a plus.

· Proven team leadership experience will be a strong plus.

· Strong programming and scripting skills in Perl, Tcl or Python will be a strong plus.

· Good communication skills and self-driven, willing to learn/share.

 

ACADEMIC CREDENTIALS:

· Master degree with 3 years or Bachelor with 5 years experience at least.

LOCATION:

· Penang

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers and will consider all applicants without regard to race, marital status, sex, age, color, religion, national origin, veteran status, disability or any other characteristic protected by law. EOE/MFDV

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Mandatory Skills: VLSI HVL Verification .

 

Experience: 5-8 Years .

 

Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention.
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