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THE ROLE:
This leader plays a key role in SoC Scan design flow, he/she will mainly focus on both tile level and chip level ATPG and verification tasks, and drive the Scan team’s execution with high quality in a good schedule manner. Moreover, he/she is expected to support post-silicon Scan ATE test to achieve the desired silicon bring up target.
THE PERSON:
Good team worker with solid scan insertion, ATPG and scan pattern silicon debug knowledge/experience. Knowledge reservation on IJTAG/Boundary Scan/BIST will be a strong plus.
KEY RESPONSIBILITIES:
· Cutting-edge test strategies study and implementation.
· Allocate DFX Scan Resource and organize periodic DFX Scan quality review
· Responsible for key design milestone DFX Scan checklist signoff
· Responsible for tile level scan insertion, quality check and ATPG.
· Responsible for scan drc check, non-scan analysis and test coverage improvement.
· Responsible for chip level scan pattern/vector generation and simulation.
· Collaborate with test engineering team to support DFX silicon bring up and ATE test.
· Drive the DFX Scan/ATPG flow robustness and efficiency enhancement.
PREFERRED EXPERIENCE:
· Solid background on process, device or ASIC design.
· Strong technical background in scan, SSN and burnin scan.
· Good knowledge on JTAG 1149.1, 1500 and 1687 protocols will be a plus.
· Good knowledge on DFT Scan/BIST will be a plus.
· Proven team leadership experience will be a strong plus.
· Strong programming and scripting skills in Perl, Tcl or Python will be a strong plus.
· Good communication skills and self-driven, willing to learn/share.
ACADEMIC CREDENTIALS:
· Master degree with 3 years or Bachelor with 5 years experience at least.
LOCATION:
· Penang
AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers and will consider all applicants without regard to race, marital status, sex, age, color, religion, national origin, veteran status, disability or any other characteristic protected by law. EOE/MFDV
Experience: 5-8 Years .
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