Job Description
Job Title:  VLSI LEAD L1
City:  Penang
State/Province:  Penang
Posting Start Date:  5/13/26
Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com.
Job Description: 

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Role Overview

We are seeking a highly skilled Senior SRAM Memory Layout Engineer with deep expertise in memory compiler layout, memory architecture development, and advanced physical verification flows. The ideal candidate brings strong full-custom layout experience using Cadence Virtuoso and a proven track record of delivering clean sign-off across advanced technology nodes.

 

Key Responsibilities

· Develop and maintain SRAM memory compiler layouts, including bitcells, periphery, and LEF views

· Perform full-custom layout design using Cadence Virtuoso

· Design and optimize critical memory blocks:

o Sense amplifiers

o Decoders

o Write drivers

o Control circuitry

· Execute and debug physical verification flows:

o DRC (Design Rule Check)

o LVS / LV (Layout vs Schematic)

o ERC (Electrical Rule Check)

o LV and RV validation

· Ensure clean sign-off across all physical verification stages

· Perform post-layout validation, LEF generation, and comparison

· Drive PPA (Power, Performance, Area) optimization

· Develop automation and flow improvements using SKILL, Python, and TCL

· Collaborate closely with circuit design, CAD, and process teams to achieve design closure

·

Required Qualifications

· 4+ years of experience in SRAM or memory layout engineering

· Strong hands-on expertise in:

o Cadence Virtuoso (layout design and debugging)

o Memory compiler layout methodologies

o Physical verification (DRC, LVS, ERC, sign-off)

· Proficiency in scripting: SKILL (preferred), Python, TCL

· Solid understanding of advanced technology nodes (FinFET preferred)

· Strong debugging and problem-solving skills

 

Preferred Qualifications

· Experience with Intel layout methodologies and validation flows

· Hands-on expertise in LV and RV validation flows

· Experience with hierarchical layout integration and sign-off

· Familiarity with Calibre, Pegasus, or ICV

· Knowledge of multi-patterning and advanced node constraints (≤7nm)

· Exposure to EM/IR analysis, LDE effects, yield optimization, and SRAM compiler or memory IP development

 
Mandatory Skills: Analog Layout .

 

Experience: 5-8 Years .

 

Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention.
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