Design Verification Engineer
Key Responsibilities:
Strong understanding of SV, UVM, and debugging skills.
Knowledge of AMBA protocols.
Develop test plans based on functional and architectural requirements.
Build UVM/System Verilog verification environments for IP/SoC testing.
Create directed and random test cases, perform coverage analysis.
Debug simulation failures with RTL designers.
Execute regression runs, analyze results, and improve processes.
Run power-aware simulations, low power checks, and work with UPF/CPF.
Collaborate with DFT/PD/RTL teams for design quality assurance.
Document test environments, plans, and results for reviews.
Experience: 5-8 Years .
Expected annual pay for this role ranges from $60,000 to $135,000 . Based on the position, the role is also eligible for Wipro’s standard benefits including a full range of medical and dental benefits options, disability insurance, paid time off (inclusive of sick leave), other paid and unpaid leave options.
Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.