RTL Design Engineer
Prefer to be in US time zones (IDC is okay, but needs to be able to stay up late to work with US folks). Ideally it’d be someone in Canada
Required: Experienced digital designer using Verilog or System Verilog.
Required: Knowledge of LINT / CDC / RDC tools
Preferred: SpyglassRequired: Synthesis Constraints for Synopsys
Preferred: Fusion Compiler
OK: Design Compiler
Knowledge of Formal Checking tools like Formality is a plus, but not required
Ability to understand, support, debug and extend existing RTL designs.
Knowledge of using GIT repositories, sharepoint for documents and scripting languages
Experience: 5-8 Years .
The expected compensation for this role ranges from CAD 77000 to CAD 120000 .
Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention.
Wipro is committed to creating an accessible, supportive, and inclusive workplace. Reasonable accommodation will be provided to all applicants including persons with disabilities, throughout the recruitment and selection process. Accommodations must be communicated in advance of the application, where possible, and will be reviewed on an individual basis. Wipro provides equal opportunities to all and values diversity.