͏

THE ROLE:

This engineer plays a key role in SoC DV flow, he/she will mainly focus on tile level scan insertion ,ATPG and scan pattern simulation. Moreover, he/she is expected to support post-silicon Scan ATE test and silicon debug efforts.

THE PERSON:

Good team worker with solid scan insertion, ATPG and scan pattern silicon debug knowledge/experience. Knowledge reservation on IJTAG/Boundary Scan/BIST will be a strong plus.

KEY RESPONSIBILITIES:

· Cutting-edge test strategies study and implementation.

· Responsible for tile level scan insertion, ATPG and scan quality check.

· Responsible for tile level scan drc check, non-scan analysis and test coverage improvement

· Responsible for chip level scan test patterns/vectors generation and verification.

· Co-work with test engineers on Scan ATE patterns bring-up, debugging and failure analysis;

PREFERRED EXPERIENCE:

· Solid background on process, device or ASIC design.

· Strong technical background in scan, SSN and burnin scan.

· Good knowledge on JTAG 1149.1, 1500 and 1687 protocols will be a plus.

· Good knowledge on DFT Scan/BIST will be a plus.

· Strong programming and scripting skills in Perl, Tcl or Python will be a strong plus.

· Good communication skills and self-driven, willing to learn/share.

ACADEMIC CREDENTIALS:

· Master degree with 1 years or Bachelor with 3 years experience at least.

LOCATION:

· Penang

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers and will consider all applicants without regard to race, marital status, sex, age, color, religion, national origin, veteran status, disability or any other characteristic protected by law. EOE/MFDV